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Recent content by 2steps

  1. 2

    how to enhance the Quality factor of a Gm-C elliptic LPF

    what do you mean by q factor of a filter hi, Increase the DC gain of integrator (Gm-C ) can enhance the Q value of filter, So you should increase the output impedance of transconductor(Gm).
  2. 2

    A kind of tuning circuit in Gm-C filter

    Hi,jecyhale Thanks for your kind help! The whole design reference paper is attached . I designed the tuning circuits based on single-end gm cell, You said this tuing circits should use balanced gm cell , I think this will be better for "master-slave" tuning. But how to transfer this...
  3. 2

    How to export GDS from Layout in Cadence? Can SKILL do it?

    export cadence layout to gds You can use cadence to stream in and stream out by GUI,just like above guy said
  4. 2

    A kind of tuning circuit in Gm-C filter

    Hi, all: I design tuning circuits for gm-c filter to compensate the gm's variation due to process,temperature and aging. My reference is form the book"Wireless.Communication.Circuits.And.Systems", and details in accessories. But I have some questions below,please help me check them...
  5. 2

    The terminal of 180 hybrid coupler

    Hi, all: I design 8GHz 180 hybrid couple using PCB microstrip to generate differential input signal to test 8GHz divider by2 circuit as figure shown,But I have a question: Is the Port 3 of the coupler is terminated by 50ohm load ,open or short ? Thanks!!!
  6. 2

    What's the significance of RPO Layer?

    resist-protection oxide silicide Yes, it is a silide blocking layer, which is named "SAB" in SMIC mapping layers, and its mask tone is dark.
  7. 2

    How to design output buffer in 8GHz divider by2

    How to design outpubuffer in 8GHz divider by2 Hi, 1.This divider's deisgn is based on 0.18um Mixed Signal/RF CMOS. 2. The divider is based on D filp-flop,realized using CML(current mode logic). and its input and output are differnential. 3. This figure is output buffer schematic from a paper...
  8. 2

    How to design output buffer in 8GHz divider by2

    Hi, All: Recently, my task is to design a 8GHz divider by2. I think it is easy to design divider core circuit, but I do not know how to design output buffer to drive 50ohm test probe. You konw, It is very sensitivity to output parasitic resistors and capacitors.I want to test this...
  9. 2

    How a substrate connection near source of the CMOS transistor reduces the latch up?

    Re: Regarding LATCHUP I think very sensitive block should be surrounded by N+ guard ring and P+ guard ring in RF circuit or others. Deep n-well is used to reduce the noise.
  10. 2

    How to simulate the sensitivity of CML latch

    Thanks, that is my question!
  11. 2

    Differential amplifier AC analysis

    dc and ac analysis of differential amplifier AC simulation is used for small signal analysis, this point is very important
  12. 2

    How to design 10kHz low pass filter without ext. large caps?

    10khz lpf For your case, the filter required is Gm-C Filter
  13. 2

    Transconductor frequency limitation on gm-c filter?

    I agreed with sixth's option
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