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LIBRARY ieee ;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
entity conterone is
port(d:in bit_vector(6 downto 0);
count:out integer
) ;
end conterone;
architecture arc_conterone of conterone is
signal x : unsigned (2 downto 0) ;
begin...
I did a program that counts the ones on a number(6 length) like 011100 the out is 3
but I want the outpot to be in bit_victor (2 down to 0) and not integer
if I input this num 011100 the output should be '011' and not 3
I im new to vhdl and need some help
how to make eight demux 2 to 1 which share same Sel ?
I did one demux 2 to 1
entity demux is
port(d,s:in bit ;
z0,z1: out bit );
end demux ;
architecture arc_demux of demux is
begin
z0 <= d and (not s);
z1 <= (d and s);
end arc_demux ;
how I can make...
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