I have built a small test board expecting to a more complete system, this board was built on single-sided copper layer using the method of photoetching, where most of the components are SMT (Surface Mount Technology).
The CPLD is a Xilinx xc9536 vq44, bought for a few euro on ebay, which i support via a JTAG interface using the Xilinx ISE tool with a programmer for parallel port. The hardware description language that i use widely is Verilog, one of the two most used with the well-known VHDL.
The card mount just 4 diodes LEDs, an expansion port, a JTAG port, 2 buttons and a reset button. The clock comes from the outside through the third pin of the expansion port, to minimize clutter also because the whole thing was built and assembled very quickly just for testing cross compatibility of HW / SW around the ISE toolchain-> Programmer -> CPLD. The clock in this case is generated by a PIC16F628 mounted on a breadboard, very simple, not crucial to describe it in detail.
Coming soon i will post full details of the experimentation board, also based on the same CPLD, but with onboard clock generation using a crystal of 4 MHz, a serial EEPROM, 8 LEDs, 4 buttons plus 1 reset, 2 seven-segment display and a small external expansion port.
Here are some pictures and a video where i show the xc9536 running a program for 4-bit binary count displayed on available 4 LEDs, occasionally interrupted by a manual reset to test the proper operation of the software and hardware.
Soon other examples that also uses the two buttons and the expansion port connected to a Hitachi 44780 controller LCD display.
A video test of sequential 4-bit binary counting.
[video=youtube;wcSeCdl0pMs]
Here is a link to the zipped file containing an EagleCad file and a pdf with good layout ready for printing on photo paper using 1:1 scale
View attachment 159897
Hope you like it.
Regards
https://riemann81.altervista.org
The CPLD is a Xilinx xc9536 vq44, bought for a few euro on ebay, which i support via a JTAG interface using the Xilinx ISE tool with a programmer for parallel port. The hardware description language that i use widely is Verilog, one of the two most used with the well-known VHDL.
The card mount just 4 diodes LEDs, an expansion port, a JTAG port, 2 buttons and a reset button. The clock comes from the outside through the third pin of the expansion port, to minimize clutter also because the whole thing was built and assembled very quickly just for testing cross compatibility of HW / SW around the ISE toolchain-> Programmer -> CPLD. The clock in this case is generated by a PIC16F628 mounted on a breadboard, very simple, not crucial to describe it in detail.
Coming soon i will post full details of the experimentation board, also based on the same CPLD, but with onboard clock generation using a crystal of 4 MHz, a serial EEPROM, 8 LEDs, 4 buttons plus 1 reset, 2 seven-segment display and a small external expansion port.
Here are some pictures and a video where i show the xc9536 running a program for 4-bit binary count displayed on available 4 LEDs, occasionally interrupted by a manual reset to test the proper operation of the software and hardware.
Soon other examples that also uses the two buttons and the expansion port connected to a Hitachi 44780 controller LCD display.
A video test of sequential 4-bit binary counting.
[video=youtube;wcSeCdl0pMs]
Here is a link to the zipped file containing an EagleCad file and a pdf with good layout ready for printing on photo paper using 1:1 scale
View attachment 159897
Hope you like it.
Regards
https://riemann81.altervista.org
