CMOS inverter

• CMOS inverter:

Fig : CMOS Inverter


Fig : CMOS inverter characteristics





Fig : Operating point of CMOS

• Propagation delay:
• The time required by the signal to propagate from input to output.
• The range of clock is considered with respect to 50% of input and 50% of output voltage transitions.
• When a logic 0 is applied to the CMOS then the load capacitor starts charging. And when logic 1 is applied to the CMOS then the load capacitor starts discharging. This charging and discharging time of a capacitor is considered as propagation delay.
• Considering 1st order Rc network the time taken by CL to charge to 50% of its final voltage is given as:

VOUT = VIN(1-e(-t/τ))
VOUT = VIN/2
VIN/2 = VIN(1-e(-t/τ))
½ - 1 = -e(-t/τ) ; Let τ = RC
Ln(1/2) = -t/RC
T = 0.69RC

• The amount of time required for the load capacitor to fully charge by the CMOS is 5τ(5RC).

Fig : Propagation delay of CMOS

• Tf = fall time; amount of time taken to move from 90% of input to 10% of output.
• Tr = rise time; amount of time taken to move from 10% of input to 90% of output.
• Techniques to reduce propagation delay:

1. Reduce CL : Remember that three major factors contribute to the load capacitance: the internal diffusion capacitance of the gate itself, the interconnect capacitance, and the fanout. Careful layout helps to reduce the diffusion and interconnect capacitances. Good design practice requires keeping the drain diffusion areas as small as possible.

1. Increase the W/L ratio of the transistors: This is the most powerful and effective performance optimization. Increasing the transistor size also raises the diffusion capacitance and hence CL . In fact, once the intrinsic capacitance (i.e. the diffusion capacitance) starts to dominate the extrinsic load formed by wiring and fanout, increasing the gate size does not longer help in reducing the delay, and only makes the gate larger in area. This effect is called “self-loading”. In addition, wide transistors have a larger gate capacitance, which increases the fan-out factor of the driving gate and adversely affects its speed.

1. Increase VDD: The delay of a gate can be modulated by modifying the supply voltage. This flexibility allows the designer to trade-off energy dissipation for performance. However, increasing the supply voltage above a certain level yields only very minimal improvement and hence should be avoided. Also, reliability concerns (oxide breakdown, hot-electron effects) enforce firm upper-bounds on the supply voltage in deep sub-micron processes.

• The rise and fall time of a CMOS is not equal because the mobility of electrons is 2.5 times faster than the mobility of holes so to ensure both the rise and fall times to be equal one has to increase the size of PMOS by 2.5 times of NMOS.
• Long interconnect wires can also affect the propagation delay. The whole net length of wire has internal RC which affects the delay.
• Power dissipation:

The power dissipation of a CMOS circuit is instead dominated by the dynamic dissipation resulting from charging and discharging capacitances.

1. Dynamic power dissipation:

Each time the capacitor CL gets charged through the PMOS transistor, its voltage rises from 0 to VDD, and a certain amount of energy is drawn from the power supply. Part of this energy is dissipated in the PMOS device, while the remainder is stored on the load capacitor. During the high-to-low transition, this capacitor is discharged, and the stored energy is dissipated in the NMOS transistor.
Dynamic power dissipation is seen only when PMOS is on and NMOS is off.
PPD ＝ VCC * IL ＝ CPD * VCC^2 * fIN

Computing the dissipation of a complex circuit is complicated by the f0 ->1 factor, also called the switching activity. Switching activity is the number of times the CMOS switches from 0 to 1 transition.

Reducing VDD has a quadratic effect on dynamic power, reducing VDD might help in reducing performance but it increases the power dissipation so when the design is power critical reducing VDD does not help. In such cases, reducing effective capacitance will improve performance and power dissipation. Reducing switching times will also reduce power dissipation but the logic of the design is given by the architectural team so having a change in effective capacitance is the main tool given in the designer's hand.

1. Direct path power dissipation:

When both NMOS and PMOS are ON we get to see direct path power dissipation as there exists a direct path from VDD to GND.
As both NMOS and PMOS are ON there exists a short circuit current and is called Ipeak.
PDP =tsc.VDD.Ipeak.f

1. Static power dissipation:

When both NMOS and PMOS are OFF we get to see static power dissipation.
In every device though it is in off state there exists a leakage current, the same is seen in OFF CMOS leading to static power dissipation.
There are 3 factors affecting the leakage current they are:

1. The reverse bias connection of PN junction leading to reverse leakage current.
2. Gate induced drain leakage.
3. Due to sub – threshold conduction.

Pstatic = VDD. Ileakage