zeros before unity gain bandwidth

[srujannnnn]

Hello all,
I am getting zeros before the unity gain bandwidth and please let me know with the methods to push the zero outside unity gain bandwidth.

 

[dick_freebird]

Often you -want- a zero to push UGBW out, your dominant
pole tending to curtail BW. The trick is keeping it from ruining
A=1 stability (if that's a design-to). You may find a need to use
two comp networks in two places, or a C and C+R in parallel.
Beware the relation of the "zero R" type you pick, to process
effects on pole position. This is why you often see the zero "R"
done as a MOSFET, for better tracking.

In the plot, your gain seems too perfectly =100dB to be an
AVOL, looks like AVCL or some other reason for 100.00dB.
The schematic shows open loop but there is something
suspiciously ideal about the DC gain result. Might check
that out.