Your verilog code style?

[NATHANHSIEH]

verilog coding style

hi all~
Everybody has style of writing the verilog by oneself, can offer the style that everybody write the procedure ?
For example form ' editor tool ' the mould group cuts apart ' in/output pin name .....

 

[kelvin_sg]

verilog style guide

A better way to learn coding style is following a conservative approach.
First start with some source codes from seniors in your company. Make
sure you code your own project with the minimum set of instructions, and
all the begin / end statements are full though many a time they can be
ignored. This is to prevent you from making mistakes since coding styles
do make synthesis differ.

Always code one instruction on a separate line.

Use tabs...

When you are familiar with Verilog, then you can learn the advanced syntaxes
and tricks... Now you can write five {} pairs on one line and not getting confused.

Use a good editor, for example Ultraedit with Verilog syntax highlighting.

Here is an article, irregular syntax causes problem.
http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf

 

[seamas]

verilog coding styles

Many EDA tools had offer a document about coding style,you can refer them.

 

[andromeda]

verilog coding standard

"Reuse Methodolgy Manual" book is the best coding style guide (it includes not only set of rules but also explanation why some rule is usefull).
OpenMORE self-assesment program (I have no idea what happened to www.openmore.com) is on-line source for rules from this book.

 

[gaonkc]

ue verilog style

you can see motorola coding style or synopsys gold document.

 

[funzero]

verilog style

Can you give me a link to Moto coding style file , thank you .

 

[haosg]

gold code verilog

don't worry of the coding style,
the synthesisaiblity and design performenct is more important,
and different eda tools prefer different coding style,
the better is accordint to synthesis tools preference.

 

[xwcwc1234]

verilog comment style

You can use EDA tool to refine the verilog coding style as you got problems. The EDA tools in the market for coding style refinement , e.g. nLint ...etc.

Added after 46 minutes:

Regarding the Verilog coding style, I upload a file " The Ten commandmnets of Excellent Design " for your reference.

 

[xworld2008]

synopsys code styles

You can use nlint to see if you verilog coding style is good , if nlint have some warning or error , u should take care it.

 

[power-twq]

rtl synthesis verilog rules

you can read the attached book and find some coding style.

hi all~
Everybody has style of writing the verilog by oneself, can offer the style that everybody write the procedure ?
For example form ' editor tool ' the mould group cuts apart ' in/output pin name .....

 

[google1983]

verilog coding guidelines

Hi all,
I think that the verilog coding styles is quite important.Your codes will be easier to read or maintain.When you work with a very big design , a consistency styles is good for you.

Regards,

 

[eexuke]

verilog multiple tabs

You can use nlint to see if you verilog coding style is good , if nlint have some warning or error , u should take care it.

I totally agree with xworld2008. But be careful, the nlint check is somehow too strict. You need to judge by yourself whether to modify the code or not according to lint tools reports. I almost never found a design passed lint check with no errors or warnings...