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I would probably transmit the 4 LVDS data lines as DDR using an LVDS clock of 125 MHz, besides the lower clock frequency sent across your twisted pair ribbon cable you'll also have the added benefit of having an easy way of determining the phase of the data for upper or lower nibble of the original 8-bit data.The configuration is going to be back to back or 3~5 cm cable.
I was thinking of LVDS interface with 4xbit, 1xclk port @250Mhz .
I would recommend that you keep the trace lengths from the FPGA(s) to the connector(s) matched to within .1 UI of the bit times. So for your 250 MHz bit times you'll want to make sure all the traces are routed with something less than 100 mil differences between all the LVDS pairs on each side of the interface between the connectors and FPGAs.In that case what are the design guidelines do i need to take into account? ( like jitter?, phase delay? Etc..)
Any idea of reference design?