buenos
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hi
lets say i have a project like this:
toplevel.vhd as top with entity name toplevel
inerface1.vhd file has an entity called interface1, and it is instantiated into topmodule as inst_interface1.
interface1 has an internal clock signal called interface1_internalclock1 running at 50MHz, and is generated in a submodule of interface1 called sub_inerface1.vhd instantiated as inst_sub_inerface1.
how do i specify the exact clock signal name in an ucf constraint file?
Im using ISE12 webpack for the development.
I have tried it in a few ways, but i always get an error saying that "NET
"xxxx" not found".
I have tried these:
a)
NET "adcif_wb_clk_o" TNM_NET = "adcif_wb_clk_o";
TIMESPEC TS_adcif_wb_clk_o = PERIOD "adcif_wb_clk_o" 20 ns HIGH 50 %;
b)
NET "Inst_s6bfip_adc/adcif_wb_clk_o" TNM_NET = "adcif_wb_clk_o";
TIMESPEC TS_adcif_wb_clk_o = PERIOD "adcif_wb_clk_o" 20 ns HIGH 50 %;
lets say i have a project like this:
toplevel.vhd as top with entity name toplevel
inerface1.vhd file has an entity called interface1, and it is instantiated into topmodule as inst_interface1.
interface1 has an internal clock signal called interface1_internalclock1 running at 50MHz, and is generated in a submodule of interface1 called sub_inerface1.vhd instantiated as inst_sub_inerface1.
how do i specify the exact clock signal name in an ucf constraint file?
Im using ISE12 webpack for the development.
I have tried it in a few ways, but i always get an error saying that "NET
"xxxx" not found".
I have tried these:
a)
NET "adcif_wb_clk_o" TNM_NET = "adcif_wb_clk_o";
TIMESPEC TS_adcif_wb_clk_o = PERIOD "adcif_wb_clk_o" 20 ns HIGH 50 %;
b)
NET "Inst_s6bfip_adc/adcif_wb_clk_o" TNM_NET = "adcif_wb_clk_o";
TIMESPEC TS_adcif_wb_clk_o = PERIOD "adcif_wb_clk_o" 20 ns HIGH 50 %;