xilinx timing constraint: how to specify object name?

[buenos]

hi

lets say i have a project like this:
toplevel.vhd as top with entity name toplevel
inerface1.vhd file has an entity called interface1, and it is instantiated into topmodule as inst_interface1.
interface1 has an internal clock signal called interface1_internalclock1 running at 50MHz, and is generated in a submodule of interface1 called sub_inerface1.vhd instantiated as inst_sub_inerface1.

how do i specify the exact clock signal name in an ucf constraint file?
Im using ISE12 webpack for the development.

I have tried it in a few ways, but i always get an error saying that "NET
"xxxx" not found".
I have tried these:
a)
NET "adcif_wb_clk_o" TNM_NET = "adcif_wb_clk_o";
TIMESPEC TS_adcif_wb_clk_o = PERIOD "adcif_wb_clk_o" 20 ns HIGH 50 %;
b)
NET "Inst_s6bfip_adc/adcif_wb_clk_o" TNM_NET = "adcif_wb_clk_o";
TIMESPEC TS_adcif_wb_clk_o = PERIOD "adcif_wb_clk_o" 20 ns HIGH 50 %;

 

[permute]

usually I try to use derived constraints. eg, constrain PAD_CLK and let the tools determine things. This allows related clocks to be constrained easily.

Another method is to look at the PAR report for things the tools call clocks. This is actually useful, as it will show you if you missed any simple constraints.

As for names, no idea. the issue is that the tools can mangle names pretty bad. the clock might end up with any number of names, like top_level_signal, instance/instance_port, instance/driving signal, signal_BUFG_O, ect... some optimizations will also destroy names. Clocks usually end up the same on each build with the same optimizations, but other nets might not.

The VHDL/Verilog and UCF "keep" (and sometimes "save") attributes can be useful

 

[rberek]

Often the synthesis tools rename signals. It may be necessary to go to the .edf file and look through it yourself. You can usually find the modules therein, and then it is a matter of finding the module you are interested in, and seeing what net names the synthesizer used to connect to the module's ports of interest. This usually works for me.
r.b.

 

[buenos]

ih there a way to prevent renaming signals?
like the syn_keep in synplify, but with XST.

The problems I can see with this method are:
-it doesnt generate an edn, it genertes i think an ngc or something.
- the netlist is like a big random character sequence, finding something in this can be difficoult
- i have around 10 clocks to constrain.

previous xilinx tools, like 6.2 worked fine with this kind of timinjg constraints, but he v12 doesnt.

---------- Post added at 10:26 ---------- Previous post was at 08:49 ----------

", constrain PAD_CLK and let the tools determine things"
im using gtp transceivers with their wrappers generated in coregenerator. the gtp has a reference clock pin and an internal pll. it generates the parallel bus clock, and thats what i want to constrain.


i have similar error for diff io clocks as well. LVDS diff data inputs from adc with diff input clock. i have specified offset in constraint, but i dont know how to refer to the diff input clock. is it clockx_P or clockx_N or clockx or what?

 

[rberek]

Well, though I haven't ever used XST, the equivalent of syn_keep is just "keep". I have found that this constraint doesn't work 100% of the time, especially if you use assigns to make two wires equal.

You can always generate an EDF file using the ngc2edf command, typed on the command line or in the SE console window. At least then you can inspect the netlist and figure out what its done with the names! I'm going from memory, but you would just type "ngc2edf blah blah", assuming you wanted to create blah.ngc from blah.edn.

r.b.

 

[buenos]

it also gives the same error (or warning if i set to egnore it) about location constraints:
WARNING:ConstraintSystem - A target design object for the Locate constraint
'<INST aurora_module_i/gtp_wrapper_i/gtp_tile_inst/gtpa1_dual_i
LOC=GTPA1_DUAL_X1Y0;> [User_Constraints/s6bf_board_constraints.ucf(296)]'
could not be found and so the Locate constraint will be removed.
i have a pci-express and an aurora interface, obviously it would be bad to swap their gtps randomly.


there has to be a general solution to "poreserve all object names"
i used the KEEP attribute in UCF and in VHDL but it had no effect.
ISE just ignores all object names that are not top level port names.
does it mean that with xilinx FPGAs we can only do single-file combinatorial logic up to an unknown speed, and the hard-IP resources are not available for the users?

 

[rberek]

Is aurora_module_i the name of the top level of the design you are constraining? If not, you may have to prepend more levels of hierarchy to the module name. This is often necessary when you generate or are given a core and its constraints, such as when you generate them from Coregen. Since Coregen knows nothing about the rest of your system's hierarchy, it can only name the module based on the part of the system that it knows about. If you've instantiated the aurora interface in your top module, the actual path name to the aurora interface might be <top_level_module_name>/aurora_module_i/....

And in answer to your first question, no there is no such constraint. As for the second question, a truly hard IP block means that it is already laid out and routed, so there is no real constraining you can do, other than from and to its IO.

r.b.

 

[permute]

one method that works well is to just build the design, then figure out what the tools did. It takes about an hour to do. Once you have the ngd you can load fpga_editor and find the names and LOC's. It also allows you to make UCF constraints for LOCs (and DIRTs if needed).

Alternatively, you can see if there are warnings for why constraints are ignored.

LOC'ing the GTP's shouldn't be required if you LOC'd the RXP/RXN and TXP/TXN. these connections don't route anywhere other than the connected GTP tiles, and the tools should be able to easily determine this. (the other case is also true -- if you loc a GTP tile, you won't need to LOC the RXP/RXN's)

 

[buenos]

ok.

what if i LOC the gtp pins and not the gtp tile? will it force the gtp tile to that location? i hope so.

about the timing constraint name errors: i think i have to make ise to ignore the constraints, so i can reach the point in the implementation process where i already have access to the constraint editor where it shows the available clock names in a list. its very stupid that in ise to be able to set up timing constraints, you need a design free of timing errors...

to preserve hierarchy, i tried this:
attribute keep_hierarchy : string;
attribute keep_hierarchy of s6bfip_dsp: entity is "yes";
in every submodule's toplevel file. i have tried it before the entity declaration, after entity before architecture, after architecture name before begin... but ise gave me errors saying its is not in the section it expects it to be. where exactly does this have to be? between which keywords?
I have specified keep for nets and i didnt get error for them, just the synthesiser removed the net names anyway.