panospet
Newbie level 3
Hello,
This is my pitch shifting effect implementation View attachment implem.rar, tested and working correctly, during simulation in simulink. But when I download this in my xup virtex ii pro board, it seems that the upsample/downlsample blocks that I used do not work. My output sounds exactly like it is before these two blocks.
Any ideas of what am I doing wrong?
When I simulate my design in simulink (for_simulation.mdl), my global clock rate is different than the one in my design for download (audio.mdl). The value Tsysclk in the second one is 1/24000000, to have a 24Mhz fpga clocking.
thank you in advance,
panospet
This is my pitch shifting effect implementation View attachment implem.rar, tested and working correctly, during simulation in simulink. But when I download this in my xup virtex ii pro board, it seems that the upsample/downlsample blocks that I used do not work. My output sounds exactly like it is before these two blocks.
Any ideas of what am I doing wrong?
When I simulate my design in simulink (for_simulation.mdl), my global clock rate is different than the one in my design for download (audio.mdl). The value Tsysclk in the second one is 1/24000000, to have a 24Mhz fpga clocking.
thank you in advance,
panospet