Zerox100
Full Member level 6
Dear my friends,
I have a created a soc project using vivado 2018. I have added an accelerator as an IP to main cpu of soc.
My problem is that when I synthesis the accelerator as a separate project (mode outofcontext) it uses 57000 LUT in synthesis. But when I add it to my design as IP it uses 65000 LUT in synthesis that is more than FPGA resources.
I have analyzed the synthesis details. Each part takes 10-15% more resources. Anybody knows any solution to my problem?
THX
I have a created a soc project using vivado 2018. I have added an accelerator as an IP to main cpu of soc.
My problem is that when I synthesis the accelerator as a separate project (mode outofcontext) it uses 57000 LUT in synthesis. But when I add it to my design as IP it uses 65000 LUT in synthesis that is more than FPGA resources.
I have analyzed the synthesis details. Each part takes 10-15% more resources. Anybody knows any solution to my problem?
THX