CADDevil
Member level 5
data2bram
Hello,
I have one problem.
I am trying to simulate and synthetise the PIC16F84 into Spartan2 FPGA. The implementation of the PIC (I got it from Opencores) use BlockRAM as a program memory.
I would like to know, how I can convert the PIC program (written in MPLAB) from HEX format into Verilog source which I can use for BlockRAM initialisation during emulation and during synthesis and bitstream generation.
I tried to search the Xilinx Web site, but I did not find any solution.
Thx for any help
CADDevil
Hello,
I have one problem.
I am trying to simulate and synthetise the PIC16F84 into Spartan2 FPGA. The implementation of the PIC (I got it from Opencores) use BlockRAM as a program memory.
I would like to know, how I can convert the PIC program (written in MPLAB) from HEX format into Verilog source which I can use for BlockRAM initialisation during emulation and during synthesis and bitstream generation.
I tried to search the Xilinx Web site, but I did not find any solution.
Thx for any help
CADDevil