xie.qiang
Junior Member level 1
x_lut4mux16
Hi guys,
when I do post-sim for Xilinx device on Modelsim, although I have compile all
the libs, but it reported that "Instantiation of 'X_LUT4MUX16' failed. The design unit was not found", and I have check all the simulation lib of "
#vlib C:/Modeltech_6.3d/xilinx_libs/UNISIMS_VER
#vlib C:/Modeltech_6.3d/xilinx_libs/SIMPRIMS_VER
#vlib C:/Modeltech_6.3d/xilinx_libs/UNI9000_VER
#vlib C:/Modeltech_6.3d/xilinx_libs/XILINXCORELIB_VER"
There is not any unit about 'X_LUT4MUX16', so I want you guys help me where I can find the design unit of ''X_LUT4MUX16' and then I can complete the simulation.
Again, I checked the source of Xilinx's simulation lib file under "C:\Xilinx92i\verilog\src\simprims", I can not find any simulation model about ''X_LUT4MUX16' , but I checked the netlists file after Place&Route, there is ''X_LUT4MUX16' in the netlists.v.
So, I am wonder if there any simulation lib does not included but P&R will actually genereted. It's so confused about that...
Thanks fou your help.
Regards,
Chris.
Added after 4 hours 48 minutes:
Hi, i have sove the problem, it is because i missuse the file for post simulation.
And the file xxx_sta.v is not for post-sim, after replaced by xxx_timesim.v, it sovled.
By the way, you guys need to change the search path for xxx_timesim.sdf in the xxx_timesim.v file.
Or else, it will report "can not parse *.sdf" when do simulation.
Regards,
Chris
Hi guys,
when I do post-sim for Xilinx device on Modelsim, although I have compile all
the libs, but it reported that "Instantiation of 'X_LUT4MUX16' failed. The design unit was not found", and I have check all the simulation lib of "
#vlib C:/Modeltech_6.3d/xilinx_libs/UNISIMS_VER
#vlib C:/Modeltech_6.3d/xilinx_libs/SIMPRIMS_VER
#vlib C:/Modeltech_6.3d/xilinx_libs/UNI9000_VER
#vlib C:/Modeltech_6.3d/xilinx_libs/XILINXCORELIB_VER"
There is not any unit about 'X_LUT4MUX16', so I want you guys help me where I can find the design unit of ''X_LUT4MUX16' and then I can complete the simulation.
Again, I checked the source of Xilinx's simulation lib file under "C:\Xilinx92i\verilog\src\simprims", I can not find any simulation model about ''X_LUT4MUX16' , but I checked the netlists file after Place&Route, there is ''X_LUT4MUX16' in the netlists.v.
So, I am wonder if there any simulation lib does not included but P&R will actually genereted. It's so confused about that...
Thanks fou your help.
Regards,
Chris.
Added after 4 hours 48 minutes:
Hi, i have sove the problem, it is because i missuse the file for post simulation.
And the file xxx_sta.v is not for post-sim, after replaced by xxx_timesim.v, it sovled.
By the way, you guys need to change the search path for xxx_timesim.sdf in the xxx_timesim.v file.
Or else, it will report "can not parse *.sdf" when do simulation.
Regards,
Chris