Xilinx ISE WebPack 11.1 , startup clock options

[cyboman]

i'm new to digital design and fpgas. i have started using Xilinx ISE WebPack 11.1 (instead of Aldec Active HDL 7.1 SE) for synthesis and implementation on Nexys2 board. i'm trying to figure out what startup clock option is and what it is used for. the tutorial i went through simply told me to use JTAG as a startup clock but it was not explained why. the options that i have available for startup are: JTAG, CCLK and User clock. i'd would really appreciate an explanation about the difference between these clocks, how i can supply these clocks to my design and why i need to use JTAG?

thanks in advance.

 

[mux_master]

startup clock options

It is the clock used during the FPGA configuration process that determines when the FPGA switches from configuration mode to user mode. So if you are going to configure the FPGA out of the external flash, for instance, you would use the CCLK. See the configuration guide for more information:
https://www.xilinx.com/support/documentation/user_guides/ug332.pdf

 

[cyboman]

Re: startup clock options

It is the clock used during the FPGA configuration process that determines when the FPGA switches from configuration mode to user mode. So if you are going to configure the FPGA out of the external flash, for instance, you would use the CCLK. See the configuration guide for more information:
https://www.xilinx.com/support/documentation/user_guides/ug332.pdf

i searched though the user guide and there are a few things that are unclear:
1) what is a user mode vs a configuration mode?
2) what do you mean by external flash? do you mean external flash memory?

thanks

 

[mux_master]

startup clock options

1) I've never used User Mode before, but I think you can generate the startup clock inside the FPGA user logic if you want to.
2) Yeah I'm talking about an external flash memory where you would store the FPGA configuration