Xilinx ISE Web Edition - Schematic problem after Synthesis

[graphene]

Once I synthesise a code with an entity and module, the RTL schematic and technology schematic comes with a black box of input and outports.

However, when I change the ports or lets say add/delete ports they dont get updated in Xilinx ISE webedition 14,7 after synthesis.

I tried clearing the cache through Project > cleanup files. Still no go.

It reallys drains my time and everytime I had to create a new project just for this reason. Any suggestion?

Thanks in advance.

 

[ads-ee]

Very difficult to debug, without more information. Perhaps you can post screen captures from the Snipping Tool (assuming Win7) to show what you mean by black box of inputs/outputs.

For the add/delete ports you probably let the tool add your files to the project and it copied them to some project folder, so if you edit your version it's not editing the copied version ISE is using.