writing output data from FPGA into a file in PC

[vipinlal]

Hi guys,
I have a designed a module which outputs a single bit in each clock cycle.I want this module to run for sufficiently long time and process the data later using some other software.I want something like writing the output data into a text file in PC connected to the board. Ho do I do this?
I am not talking about simulation here.I want the code to run in real time on a fpga board.

Any suggestions are welcome. If there are standard programs available for this online then please post the link also.

I just searched in net.And I found that I can use RS232 port available on the spartan-3A starter kit board.But I dont know how to use it. Can somone write a step by step procedure for this?

thanks,
vipin

 

[Jack// ani]

Well, you didn't mention bandwidth of your data.

Anyways, that's not a big issue here. You need to implement UART for RS232 interface, free ones are available here: **broken link removed**

Once you have RS232 in place, you can capture data on your PC by bunch of tools....like MATLAB or some other RS232 terminal software.

Good luck

 

[vipinlal]

Thanks Jack for the reply.

My data bandwidth is between 10MHz and 50MHz.

How do I implement the UART for the RS 232 interface.As per my knowledge UART have different standards.So how do I know which standard to be used.
And also how do I select the baud rate.

 

[Jack// ani]

Link I provided you above has HDL description for UART, go through the datasheet for its implementation details.

You have to provide appropriate baud-rate, depending on clock frequency used by FPGA board.

Then all you do is throw in your data and it will come out from your RS232 port.

 

[vipinlal]

Thanks again.

I went through the documentation. But there is no information about the below ports in the doc. Can you tell what these signals mean or where I can find more info about it?

input [13:0] csr_a,
input csr_we,
input [31:0] csr_di,
output reg [31:0] csr_do

I dont even know the full form of the "csr".

 

[permute]

vipinlal,
RS232 is slow. you likely won't be able to transmit at 10-50 mbps. USB might be able to work, but would need to be set up correctly.

For your question -- csr_a/we/di/do defines an internal bus structure suitable for memory-mapped IO with a soft-core CPU. there is a csr.pdf in the linked site.

There should be many UART cores in both VHDL and Verilog. Its a very common and easy to write function. but, as mentioned, you'll probably be limited to something closer to 100-200kbps.

 

[eltonjohn]

you need to buffer the data in a FIFO and then to use a HI speed USB device like the new ones from FTDI

 

[vipinlal]

I think I will stick with RS232. dont want to make things complicated for now.

Jack, the project link you have shard looks little bit complicated to me.I wont be using the CSR feature at all.So I found another project here:
https://opencores.org/project,miniuart2

The core is in VHDL and is wishbone complaint. The interface looks pretty simple in this case.I will try this for now.Thanks guys..

 

[ckaa]

Another suggestion - If by chance you are using an Altera device, there is a UART ip core included and you could use the NIOS and some C code and implement the whole UART pretty easily, can skip the whole implementing the UART in HDL phase.