why using Buffer after ADC

[itmr]

HI ALL
i am fpga design engineer and i have a little question for you - why using op amp as buffer after adc

the main reason i guess is to increase the gain - but some one toldme that its good for data acquisition and i didn't understood why???

does somebody can help me to understand it?

thank u all

 

[FvM]

Do you mean a buffer amplifier in front of the ADC? What's the ADC's sampling rate? Did you know the suggested source impedance for achieving full ADC performance?

 

[itmr]

FVM - i know that buffer amplifier in front of ADC suppose to increase the gain of the input signal - that comes from any sensor 4 example.
my question refer not to specific adc or specific sampling rate - i mean i just want to know what the needed of output buffer 4 ADC when the adc connected to FPGA - i guess that there are 2 reasons - the first is to equalization the voltage level ( adc plot samples with 3.3v and FPGA suppose to get 1.8 v ...) the secound is to avoid any fail in the FPGA WHEN THE adc faild or some thing.

did you have more reason to this output buffer?

 

[JayantD]

Upload your schematic.

 

[itmr]

this is the scheme

 

[JayantD]

That's a low pass filter BEFORE the ADC.
That it has been drawn after the ADC doesn't mean it is after the ADC. Follow the signal flow.

 

[itmr]

JayantD you right but there is buffer after the adc -named NL27WZ17DF - LOOK AT THIS...IT CONNECTED TO THE SERIAL DATA THAT COMES FROM THE ADC

 

[JayantD]

itmr,
NL27WZ17DF is a dual non-inverting Schmitt triggered buffer, not an op amp. If the Vcc (pin 5) of this part (not shown on your schematic) is 1.8V, it is used as a level translator 3.3V to 1.8V. It has overvoltage tolerant inputs. So even if it is powered by 1.8V, it will tolerate 3.3V signal outputs of the ADC.
See datasheet at NL27WZ17DFT2 pdf, NL27WZ17DFT2 description, NL27WZ17DFT2 datasheets, NL27WZ17DFT2 view ::: ALLDATASHEET :::
Hope this helps,
JayantD

 

[FvM]

Level conversion of digital signals may be required in some cases, but you have been asking for an op amp buffer.

 

[leelsuc]

this is a noise consideration. i.e. isolate noise coupling from fpga to adc. when you calculate your adc accuracy spec, you will need to consider buffer or nonbuffer architecture.