Why this topology is called a comparator?

[zhangseong]

why is this topology is called a comparator ? how the circuit perform , what is the 1st part of the circuit ? is it an inverter?

 

[barath_87]

Re: comparator

Can you please specify where are the two inputs...Of course the last part of the circuit is a cmos inverter....

 

[pankajdudulwar]

comparator

which quantitys u want to compare ............

 

[gingerjxb]

Re: comparator

maybe the reference voltage is regarded as the MOS threshold.
the first stage is a pre-amplifier stage

 

[rmadhukarthi]

Re: comparator

the first stage is the resistively loaded comon source amplifier stage.

 

[haoshs]

comparator

it's a single-Ended comparator. it 's just is a buffer.
the threshold of comparator(not nmos) varies along with process!

 

[hung_wai_ming@hotmail.com]

comparator

If you need to regard this as comparator, then the trip point is the inverter trip point where it can switch from L to H. Then first stage determines when to turn over when the INPUT is switching from VSS to some point (say, VDD/2) where parallel equivalent resistance of the RDS of NMOS and the up resistor is equal to the trip point of inverter, then the inverter turns from L to H, that's the comparison happens.

 

[zhangseong]

Re: comparator

hey guys, thanks for the valuable answer especially hung_wai_ming@hotmail.com
...

 

[suria3]

Re: comparator

If you need to regard this as comparator, then the trip point is the inverter trip point where it can switch from L to H. Then first stage determines when to turn over when the INPUT is switching from VSS to some point (say, VDD/2) where parallel equivalent resistance of the RDS of NMOS and the up resistor is equal to the trip point of inverter, then the inverter turns from L to H, that's the comparison happens.

Hi,

As we know that the trip point of a inverter is VDD/2, then in order to be the trip point voltage, the common source amplier effective dc voltage is designed at VDD/2. Then as the common source dc voltage increase or decrease from VDD/2 will trigger the inverter either to be in logic high or low.

Thx