Why Synplify can compile some VHDL sources?

[siosavin]

synplify problem.

Synplify cannot compile vhdl sources which have real divided by real statement. How i can solve this problem?

 

[wasp]

Re: synplify problem.

The type of the data real does not enter into a synthesized subset of language VHDL.
Try to present your data in the other kind.

 

[siosavin]

synplify problem.

It support REAL data. It can add, sub, multiply to REAL.
But it cannot divide two REAL. I want a solve for it.

 

[wasp]

Re: synplify problem.

Synplify does not support type of data REAL. You are mistaken.
Otherwise result to me the FULL REFERENCE on the documentation where it is told about the opposite.

 

[Aser]

Re: synplify problem.

Real numbers are not mapped directly into hardware now
because of complex resulting netlists.
But when specifying constants
one can do some calculations with real numbers,
and the resulting constants have to be integers or vectors
which are synthesable.
Synplify could do such constants except calling procedures with
real numbers because it does not port the library IEEE.MATH.REAL, etc.

 

[delay]

Re: synplify problem.

I concur with Wasp. Synplify does not support real types. Just declare a type pi as real in a package and you will get an error. Use Leonardo Spectrum for real types.

delay (delayed by technology)