why should we set clock margin in constrain file when systhesis?

[ciciw]

hi all,
i want to ask a simple question,
why should we set clock margin in constrain file when systhesis?

and the typical value of the margin should be ?

thanks all...

 

[ciciw]

could anyone help me on this? thanks very much!

 

[vijayR15]

hai ciciw

Generally we use this for tightening the constraint... Reducing the time... Making the tool to meet the timing....... The value for the margin we set is based on the size of your design also we will give very less value for this...

Hope this may help you.. Thanks

 

[ciciw]

hi vijayR15,

thank you...
and i have seen an example: clock period=15ns, and in the constrain file, it will set clock_margin=0.85(15% margin), and the actual clock period used in the design is:15ns*0.85=12.75ns, so it is over-constrain,just like you said.

"The value for the margin we set is based on the size of your design" ----------what does this mean?
another question:when doing STA, i think the constrain file should be the actually value of clock (15ns), am i right?

thank u....

 

[vijayR15]

hai ciciw...,
Exactly u r right............ "size of the design" in the sense i represented the time period only.....

when doing STA, i think the constraint file should be the actually value of clock (15ns)?

Actually watz your aim here is making your design to work in 67mhz......... but u tightened the constraint i.e u r reducing your time period In the sense u are trying to make your design work even in 78mhz i.e (12.75ns). Its an added advantage if u reduced slack for this then your design will function correctly upto this frequency.

So During STA here they used 12.75ns to meet the best timing....

Basically wat i do is i will use the same sdc file for STA and i will tighten the constraint by setting uncertainity.......


This may help thanks:razz:

 

[ciciw]

yes...i have also seen set_clock_uncertainty in the sdc file...
so...the clock margin and clock uncertainty have nearly the same function in our sdc file?

but, the clock margin is used in both setup &hold timing(for it does not point to setup or hold seperately), for clock_uncertainty, u can use set_clock_uncertainty -setup/-hold, so u can use different uncertainty in setup and hold.

and i have seen: normally set_clock_uncertainty, for -setup option, use a larger uncertainty(i.e 0.750), for -hold option, use a less uncertainty(i.e 0.075),could u please kindly expain more about this? does that mean we should focus more on setup timing?

thank u very much...i have learned a lot from your reply!

 

[vijayR15]

hai ciciw: -

Noramlly we fix hold by command. using this maximum hold violation will be cleared so there is no need of concentrating more on hold... In Bestcase we will deal with hold violation.. Also be cautious if there is hold violation then your chip will not work...

In worst case there will be more setup violation... so once we cleared worst case maximum violation in bestcase will also be cleared.. So only we are concentrating more on setup..

hold will be fixed by tool itself... That is the reason we are not focusing more on hold

This will be little clear to you.. Thanks

have fun ciciw.............:razz:

 

[ciciw]

hi vijayR15,

thank u very much!