asicguygmail
Newbie level 4
Hi,
I synthesize an RTL code with Synopsis. I add a wire_load_model to my synthesize process. At the end I do a report_timing and I see all gate delays but I don't see any net (wire) delays in the timing paths.
This is the command that I use to add wireloadmodel:
set current_design cnode
set_wire_load_model -name "TSMC8K_Lowk_Aggresive"
Why there is no delay associated with wires between gates?
Do the gate (cell) delays include the wire delays or they will show up after place and route and the delays that I see must be mutiplied by a factor bigger than 1?
Following commands didn't help neither and I still don't see wire (net) delays:
set auto_wire_load_selection true
set_wire_load_mode enclosed
Thanks for any help and feedback
Dave
I synthesize an RTL code with Synopsis. I add a wire_load_model to my synthesize process. At the end I do a report_timing and I see all gate delays but I don't see any net (wire) delays in the timing paths.
This is the command that I use to add wireloadmodel:
set current_design cnode
set_wire_load_model -name "TSMC8K_Lowk_Aggresive"
Why there is no delay associated with wires between gates?
Do the gate (cell) delays include the wire delays or they will show up after place and route and the delays that I see must be mutiplied by a factor bigger than 1?
Following commands didn't help neither and I still don't see wire (net) delays:
set auto_wire_load_selection true
set_wire_load_mode enclosed
Thanks for any help and feedback
Dave