why my sram cell does not store any value?

[kpkp]

Hi everybody, i'm making analog design of 6t SRAM cell in cadence. but my cell does not store the value 0 or 1 inside the cell. when i apply complementry values to bit line (Vdd) and bit_bar (gnd) line it keeps the value storing inside bt as i remove the voltage it takes the value of power supply. that means it does not store the values applied at bit line and bit_bar line...can anybody help me??? I have attached my schematic also herewith...

Thnx in advance...

 

[varunkant2k]

I don't see any problem, in fact I am getting correct result in my simulation. I see nothing wrong except NM2 that is source and drain you can change. But That should not affect the result. Please check the models file if you have chosen correctly.

 

[kpkp]

Hello, thanks a lot for answer. I have solved the problem in writing operation. But now i am facing problem in reading operation. Actually i want to measure delay in read operation. so can you please help me in completing the read circuit??? I want to disconnect the data lines from cell while precharge voltage is on to charge the data lines. Therefore i have used tristate buffer which is disabled when precharge voltage is on , But I'm getting errors ... so can you please suggest me some changes or else? schematic has been attached herewith....

Thanks in advance....

 

[varunkant2k]

What the errors you get? This is just the logical implementation.

 

[kpkp]

I got errors due to tristate buffer...Do you know how to configure the buffer or inverter ??
error says that netlist cannot be generated...
Thnks...

 

[varunkant2k]

You can create your own tristate buffer. Try to use that. I prefer to use pass transistor gates for that.

 

[kpkp]

yeah exactly. After that I have already tried pass transistor and i got the desired outputs...
but can you please tell me from which waveform I should measure the read delay? I mean to say from bit lines or from q and q_bar points? I have attached my waveforms here...Between 5 ns and 6 ns, when word line (WL) has been raised, the bit_bar has been discharged and bit line is still at high potential...so is it appropriate waveform to calculate the read delay?

Thanks....