kumar123
Member level 3
Hi,
I have designed (Nmos input current mirror o/p stage) Folded cascode signle ended stage, after doing simulations i have observed different issue like
it can operate over Vcm of 0.75 to 1.8V (as supply vltage is 1.8V)
with this Vcm i am varying Vdiff also to make sure till what value all transistors are in saturation.
IP = Vcm + Vdiff
IN = Vcm - Vdiff
Vdiff -----> vary from -50mV to +50mV @ different Vcm
1st Experiment:
Vcm = 0.75 Vdiff vary between -50mV to +50mV
Results: all transistors are in saturation between -1mv to +1mv
2nd Experiment:
Vcm = 1.8 Vdiff vary between -50mV to +50mV
Results: all transistors are in saturation between -0.25mv to +1.75mv
why is the shift from left to right (instead of uniform around Vdiff =0 Axis) as Vcm changed to some high value?
can any one comment on this ?
I have designed (Nmos input current mirror o/p stage) Folded cascode signle ended stage, after doing simulations i have observed different issue like
it can operate over Vcm of 0.75 to 1.8V (as supply vltage is 1.8V)
with this Vcm i am varying Vdiff also to make sure till what value all transistors are in saturation.
IP = Vcm + Vdiff
IN = Vcm - Vdiff
Vdiff -----> vary from -50mV to +50mV @ different Vcm
1st Experiment:
Vcm = 0.75 Vdiff vary between -50mV to +50mV
Results: all transistors are in saturation between -1mv to +1mv
2nd Experiment:
Vcm = 1.8 Vdiff vary between -50mV to +50mV
Results: all transistors are in saturation between -0.25mv to +1.75mv
why is the shift from left to right (instead of uniform around Vdiff =0 Axis) as Vcm changed to some high value?
can any one comment on this ?