Why do we use dynamic logic?

[engrbabarmansoor]

why do we use dynamic logic?What are its advantages and disadvantages?

 

[ezt]

Re: dynamic logic

Hi engrbabarmansoor,
As far as I know, it's first advantage is less number of transistors which results in less area or higher density in the same area compared to conventional static CMOS logic. BTW, the dynamic logic is actually an improved version of conventional ratioed logic which uses a fixed resistor as the pull-up network (in case of static nMOS complementary logic as the pull-down network). In dynamic logic, a clocked pMOS is used instead of the fixed resistor. Hence only when it is required (the pull-down network is OFF) the CLK which drives the gate of this pMOS is set to LOW and the output is shorted to VDD. In this case the total power consumtion is reduced considerably compared to conventional ratioed logic which has a static power dissipation whenever the pull-down network is working (ON).
On the other hand, its fewer number of transistors in pull-up network (compared to static CMOS logic), results in smaller load capacitor (with the same transistor sizes) and may result in higher speed (smaller delay) compared to static CMOS logic. (However its power consumption is usually larger than its static CMOS counterpart).
An improvement of this logic would be domino logic.

Regards,
EZT

 

[maharshi_qis]

Re: dynamic logic

Dynamic logic uses the parasitic capacitance for deciding logic level..
it requires less no. of transistors..
it is very faster in operation..
power consumption is less.
delay is less..
ratioed logic...

 

[shivanand_bhavi]

Re: dynamic logic

Dynamic Logic is faster than Static CMOS. Moreover different styles of Dynamic logis makes even faster like Domino, Zipper.

IN dynamic Cmos you rarely use PMOS ,PMOS tree

 

[engrbabarmansoor]

Re: dynamic logic

Thanks for reply !

 

[eternal_nan]

dynamic logic

Just to complete the discussion:

Dynamic logic is pretty much never used in modern processes (<0.13um) since it is hard to get to work properly. If no keeper transistor is used the gates are very sensitive to any form of noise and, additionally, the leakage through the 'evaluate' network can easily discharge the 'state' capacitor if clock cycle is at all long. If a keeper is used, it is hard to make it sufficiently strong to combat leakage AND possible to overpower it when evaluating when uncorrelated process variation of n and p transitor parameters is assumed.

All in all, dynamic logic is on its way out (and is largely already there).

 

[quantized]

Re: dynamic logic

Just to complete the discussion:
Dynamic logic is pretty much never used in modern processes (<0.13um)

All in all, dynamic logic is on its way out (and is largely already there).

Hogwash. The CPU in every iPad and iPhone made in the last four years uses domino logic for its critical path. Apple bought an entire company in order to get their 1-of-4-rail domino logic toolchain.

All the Achronix chips made on Intel's 22nm fab line are entirely dynamic logic, although the company goes to great lengths to avoid mentioning it.

All that's changed is that the keeper which used to be optional is now mandatory, and as a result there are lots of interesting schemes for reducing the overhead imposed by the keeper. That's it.

Domino/dynamic logic didn't become less attractive, but a lot of "push button get chip" tools appeared that can only do static CMOS. The performance gap is still there, there's just more people/teams stuck on the bottom end of the gap.