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Kul_priya said:I am very new to STA & PT. I just started with PT, i am using the same constraints as given to DC. I am getting violations in PT and no violations in DC.
I did a small study and found that the violations in PT are because, we are giving min & max latencies for the clocks while we do create_clock. DC is taking same latency for both Launch & Capture paths but PT is taking the max value for the Launch path and min value for the Capture path (which is the worst case and PT is doing the right thing i guess). This PT run is just after synthesis even before CTS is done, so what is the significance of this min & max latencies? We have given max latency as 1.20ns & min as 40% of it i.e. 0.48ns which is making a difference of 520ns?
Also in PT if the analysis type is set as bc_wc or single, PT also considers same clock latency for both Launch & Capture, but for OCV it takes min 7 max values as said above. So do i need to fix the violations? are they real?
Sorry for the long mail