Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why do we need DC if we can only use PT for synthesis?

Status
Not open for further replies.
DC vs PrimeTime

its nt possible to do synthesis in PT...
thats true...

shiv
 

DC vs PrimeTime

hi dozy,


PT means Prime Time.......

as all are discussing its used for Timing analysis
 

Re: DC vs PrimeTime

I am very new to STA & PT. I just started with PT, i am using the same constraints as given to DC. I am getting violations in PT and no violations in DC.

I did a small study and found that the violations in PT are because, we are giving min & max latencies for the clocks while we do create_clock. DC is taking same latency for both Launch & Capture paths but PT is taking the max value for the Launch path and min value for the Capture path (which is the worst case and PT is doing the right thing i guess). This PT run is just after synthesis even before CTS is done, so what is the significance of this min & max latencies? We have given max latency as 1.20ns & min as 40% of it i.e. 0.48ns which is making a difference of 520ns?

Also in PT if the analysis type is set as bc_wc or single, PT also considers same clock latency for both Launch & Capture, but for OCV it takes min 7 max values as said above. So do i need to fix the violations? are they real?

Sorry for the long mail :)
 

Re: DC vs PrimeTime

Kul_priya said:
I am very new to STA & PT. I just started with PT, i am using the same constraints as given to DC. I am getting violations in PT and no violations in DC.

I did a small study and found that the violations in PT are because, we are giving min & max latencies for the clocks while we do create_clock. DC is taking same latency for both Launch & Capture paths but PT is taking the max value for the Launch path and min value for the Capture path (which is the worst case and PT is doing the right thing i guess). This PT run is just after synthesis even before CTS is done, so what is the significance of this min & max latencies? We have given max latency as 1.20ns & min as 40% of it i.e. 0.48ns which is making a difference of 520ns?

Also in PT if the analysis type is set as bc_wc or single, PT also considers same clock latency for both Launch & Capture, but for OCV it takes min 7 max values as said above. So do i need to fix the violations? are they real?

Sorry for the long mail :)

DC is a synthesis tool for asic where as leonardo spectrum should be a synthesis tool for the FPGA designs.
all the synthesis tools(DC,Cadence RC, Magma) can do the timing analysis to the some extent. Basically the synthesis tools try to optimize design based on the timing/power/area constraints supplied by the user. So this timing is some what ok.
PT is purely a timing analysis tool, we do the timing analysis after the place and route so you will have complete parasitica info and the wire length, so you will have complete timing info . STA is a path based timing analysis.

We need to analysis the each path in the design into different mode like functional, test mode and so on, iof any violations you need to fix the either by upsizing the cell or polacing the buffer to meet the timing. if you the violation is too large then you need to go back to place and route or even synthesis level adjust the constraints.

OCV will provide the extra timing margins even the synthesis tools can also support the OCV measures to some extent.
 

Re: DC vs PrimeTime

for the timing analysis , the PT is more powerful! the DC is for the synthesis and make a preview of the timing!
 

Re: DC vs PrimeTime

Hi,

Being a synthesis tool, the main aim of DC is synthesis. It does require some information on timing, but it is not always required. Also custom designed moduled are implemented as such and DC cannot handle post-layout timing analysis.

PT is a good tool in the sence it has a lot of options for Timing analysis. False-paths, CDC, timing with clock phase differences, delay annotated designs e.t.c. can be handled by PT effectievely. Hence it can be used even after Place and Route. That is the reason why PT is preffered for timing analysis..

Regards,
Hareesh
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top