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Who has papers about Lateral PNP in p-sub CMOS Process?

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wells001

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Who has papers about Lateral PNP in p-sub CMOS Process? I want to design a low noise circuit.
 

In p-sub processes, lateral PNP transistors are generally not good transistors.They have small beta(less than 20-30) and processes generally don't guarantee reliability.
I use lateral PNP's in a bandgap circuit which there is no need to amplify any signals and I encounter some problems about that.

Maybe you should try HBT's.
 

They don't have as high of beta, but they do typically exhibit lower 1/f noise...
 

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