who can help me in frequcy divider?

[fiq]

Hi,
I designed a frequcy divider circuit,how can i get the sensitivity of it,that is mininum input vs frequency,how can i get it?
there is another problem,how can i know the bias voltage of the clock input node.
someone said by simulation,but I can.t understand.
thank you!

 

[willyboy19]

Your question is not clearly stated. Try again.

 

[paladinzlp]

is your frequency divider used in PLL.

 

[Tianlei]

For the 1st question, Yes it should come from simulation. High speed diveder is sensitive to the input amplitude.
You can run simulations on some interesting frequency points. For each freq point, try to find the minimus input amplitude at which the frequency divider can still work. Then you can draw a plot on minimum input amplitue v.s. freqency

 

[suromenggolo]

used wide bandwith amplifier before input to frequency divider.