ipelagic
Newbie level 3
Dear All,
I am a newbie to ic design. My question is that if I were provided with two designs. ( All written in VerilogHDL ) Is there any tool supported by Synopsys or Cadence that can help me to verify the equivalence of these two designs?
One design is in a .v file. And the other is split into several submodule (.v files) along with a top module ( _top.v ). I think there should exist a tool to help me verify the equivalence if given IN/OUT PIN mapping. Thanks in advance
I am a newbie to ic design. My question is that if I were provided with two designs. ( All written in VerilogHDL ) Is there any tool supported by Synopsys or Cadence that can help me to verify the equivalence of these two designs?
One design is in a .v file. And the other is split into several submodule (.v files) along with a top module ( _top.v ). I think there should exist a tool to help me verify the equivalence if given IN/OUT PIN mapping. Thanks in advance