Bulma
Junior Member level 2
vcs/questa for systemverilog
Hi all, I have some questions really need your helps :
I've heard of Cadence tool named IUS. It seems to strongly support SystemVerilog. Anyone here tried this tool please share your experiences ...
1. Does it support all features & constructs of SystemVerilog ?
2. Can we reuse our old design IPs in new design using this new tool ? (Not counting on some syntax error may appears).
3. How fast is its speed ?
4. Which is IUS latest verion ?
Any reply is much appreciated ! Thanks in advance !
Hi all, I have some questions really need your helps :
I've heard of Cadence tool named IUS. It seems to strongly support SystemVerilog. Anyone here tried this tool please share your experiences ...
1. Does it support all features & constructs of SystemVerilog ?
2. Can we reuse our old design IPs in new design using this new tool ? (Not counting on some syntax error may appears).
3. How fast is its speed ?
4. Which is IUS latest verion ?
Any reply is much appreciated ! Thanks in advance !