Which architecture suit for 60MSPS 6bit ADC?

[justin]

I want to design 60MSPS 6bit ADC, and the die size is in the concern. which architecture is sutiable, and could you tell me the approximate die size in 0.25um process? Maybe the flash's size is too huge in 6 bit , I think.

 

[xuel]

2-step flash

 

[derekqiao]

A brief paper to describe ADC architecture:

 

[amraldo]

if u r not concerned with area use flash or 2-step flash or folding adc
or pipelind architecture with didital assistance

 

[gevy]

I think, that best decision is pipelined ADC with digital error correction.

 

[yeewong_su]

two stage, I think the pipeline is not a good choice

 

[CDRCDR]

folding architecutre instead

 

[segabird]

if u r not concerned with area use flash or 2-step flash or folding adc
or pipelind architecture with didital assistance

Is the function of folding circuit in folding adc the same as the subdac circuit in the pipeline ad?

 

[justin]

Thanks for all!
Because we don't know the real die size and we maybe take a long time to design the ADC, we change the system. And we don't use ADC now.

 

[cetc1525]

we have designed a 8bit AD using flash .