Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Where to see fmax for each clock domain in Xilinx ISE

Status
Not open for further replies.

cafukarfoo

Full Member level 3
Joined
Jul 25, 2007
Messages
170
Helped
8
Reputation
16
Reaction score
5
Trophy points
1,298
Activity points
2,510
Hello everyone,

Can anyone share where to see the fmax for each clock domain in Xilinx ISE software?

Is it under "Timing Constraints" below the "Design Overview" category?

Thanks in advance for your help.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top