where signal routing is done in physical design flow?

[yuhiub90]

Is signal routing done on same layer with stdcells and macros?

 

[andre_luis]

signal routing done on same layer with stdcells

I was asking to myself in what sense that issue matters, taking into account that it is expected for the place-and-route CAD to make use of as many metallization layers as are available for the fabrication process specified for the ASIC device in question.

 

[ThisIsNotSam]

Is signal routing done on same layer with stdcells and macros?

depends on the technology. back in the day, you could do routing with poly. now signal routing starts at M2/M3.

 

[yuhiub90]

I was asking to myself in what sense that issue matters, taking into account that it is expected for the place-and-route CAD to make use of as many metallization layers as are available for the fabrication process specified for the ASIC device in question.

I'm wondering because in power planning, power/ground rails are created on same layer with stdcells. It will block the routing path if signal routing is done here.

 

[ThisIsNotSam]

I'm wondering because in power planning, power/ground rails are created on same layer with stdcells. It will block the routing path if signal routing is done here.

std cells are drawn with the rails already. your worry is not a concern at all.

 

[yuhiub90]

std cells are drawn with the rails already. your worry is not a concern at all.

I know. But Talus requires power/ground rails to insert filler cells. Once created the rails expand over whole stdcell row to tap with upper power network (mesh, ring).

 

[ThisIsNotSam]

I know. But Talus requires power/ground rails to insert filler cells. Once created the rails expand over whole stdcell row to tap with upper power network (mesh, ring).

yes, as it should.