Whats the difference between Verilog and VHDL ?

[shiningblue]

verilog and VHDL

What is the difference between these two? which one is useful or popular?

verilog HDL means verilog or vhdl?

it might be a stupic question, but thanks for your answer.

 

[eltonjohn]

Re: verilog and VHDL

This is a very asked question .Several times we have debated about it .
No need to start over and over ..
Do some search at EDA all is here
HDL is both verilog and VHDL ..as well as others AHDL etc

 

[eltonjohn]

Re: verilog and VHDL

VHDL = VHSIC hardware description LANGUAGE
VHSIC = Very High Speed Integrated Circuit

 

[Prashant Mishra]

Re: verilog and VHDL

both are hardware description langauge.veriolg is similar to C langauge and VHDL is like ADA.
verilog HDL means verilog langauage.
both are popular and useful.

Added after 1 minutes:

both are hardware description langauge.veriolg is similar to C langauge and VHDL is like ADA.
verilog HDL means verilog langauage.
both are popular and useful.

 

[crazy_man]

Re: verilog and VHDL

both are used for designing logic..
Invariably the selection of the language depends on the vendor..
Not much difference between the two...
VHDL is more elaborative than verilog. I have felt that VHDL is a lot more easy to understand than verilog.. But seriously, there is no much difference between the two..

 

[smith_kang]

Re: verilog and VHDL

hi
verilog and VHDL are both Hardware Description Langauages.
Verilog and VHDL both are now industry standard for writing code for Hardware.
Verilog is very much close to C langauge and VHDL is close to PASCAL.One thing you must remember VHDL is very strongly typed langauge and you must follow the rules accordingly.
Verilog is simple to learn.You can start with this langauge.

 

[j2005]

Re: verilog and VHDL

I have coded with both before and seriously, I don't see much difference other than the syntax. You know one, and you'll pick up the other easily. At the end of the day, just learn whatever your school/ work uses.

 

[arp]

Re: verilog and VHDL

if u r good in C then u feel verilog is easier one otherwise VHDL is easy.

in my view for learners VHDL is easier one but when u go for big designs u feel uncomfortable by using this unless u know syntaxes correctly
anyway i feel VHDL is easier than verilog.
whats ur views

 

[laocai]

Re: verilog and VHDL

i think verilog is easy to use

 

[mipedja]

Re: verilog and VHDL

VHDL is familiar with ADA
Verilog is familiar with C

 

[shashi_reddy21]

Re: verilog and VHDL

VERILOG and VHDL both are used for coding ,but recnetly i found that most industries use VERILOG only.

 

[ikru26]

Re: verilog and VHDL

Both VHDL and Verilog are Hardware discription languages and compatable with simulation and synthesis tools. There are some abstraction levels of any digital design as system level(top level OF abstraction ), then module level, gatelevel, circuit level, device level.
In VHDL we can write the program upto gate level only and also we can see the hardware upto gate level only but in Verilog we can write the code and see the harware upto circuit level. this is the main difference between them. there are some more differences , i will tell you if you are more interested.

 

[subdural]

Re: verilog and VHDL

Since both VHDL and Verilog is HDL, is that possible to interfacing or convert both language to be understand each other? Any tools can do this?

 

[omid219]

verilog and VHDL

there are some tools for C to VHDL/Verilog conversion, but have not seen such a this software for VHDL 2 Verilog conversion.
BTW, I myself have worked with both VHDL & Verilog, I think coding time in verilog is less than vhdl.

 

[bloodemon]

Re: verilog and VHDL

I think both of the languages are useful, once you know one well, you can pick up the other one easily. However, they do have some difference, here is a good comparison article, maybe you can take a look.