ishan.dalal
Newbie level 5
I came across one of the answers of this question in one of the threads.
"Critical path in the SRAM is activated when a logic 1 is read from the cell at the first row's last column. This constitutes the critical path because when the word line is asserted from the row decoder, it has to charge ALL the gates of the pass transistors preceding the final column before the final column's pass transistors are asserted high. Likewise, after this process, when a 1 is read from this cell, it has to charge all the parasitic capacitors in the entire column before charging the read / write buffer input."
Could anyone please help me understand the bolded line?
Also if there is further explanation required for this question, please provide it.
Thanks in advance
"Critical path in the SRAM is activated when a logic 1 is read from the cell at the first row's last column. This constitutes the critical path because when the word line is asserted from the row decoder, it has to charge ALL the gates of the pass transistors preceding the final column before the final column's pass transistors are asserted high. Likewise, after this process, when a 1 is read from this cell, it has to charge all the parasitic capacitors in the entire column before charging the read / write buffer input."
Could anyone please help me understand the bolded line?
Also if there is further explanation required for this question, please provide it.
Thanks in advance