What to do with the unconnected port(input or output)?

[shabbs]

Unconnected Ports

Hai there !
Thanks for reading this post.I have query that,What should one do with the unconnected port ( input or output ).Is it ok to leave it open else if we ground it or put high value .Later in the design while using the same port.Wouldnt the output have error ?

 

[vikas_lakhanpal27]

Re: Unconnected Ports

We can leave the output Open but input shuld be tied to '0' or '1' as per our design

 

[A.Anand Srinivasan]

Re: Unconnected Ports

leaving a port unconnected would lead to noise coupling... so it is a better idea to connect it to ground or Vdd.. be it input or output..

 

[vikas_lakhanpal27]

Unconnected Ports

Anand,
can u throw some more light on noise coupling?
and 1 more doubt i dont think if we leave output open it wont affect the functality of ASIC.i have left output open so many times but i didnot face any problem .

 

[A.Anand Srinivasan]

Unconnected Ports

a unconnected wire can fluctuate in terms of voltage... the fluctuation wont be much but in terms of capacitance the fluctuations affects the nearby wires too many unconnected wires worsens the case further and would cause accumulation of noise...

 

[ramanav]

Re: Unconnected Ports

In Cmos inputs should not be left unconnected.
Output if left unconnected will give rise to crosstalk and short circuit may occur and voltage drop will be high in that net.

 

[kumar_eee]

Re: Unconnected Ports

How this noise analysis & Signal integrity calculations are being done?.

 

[kimhj103]

Unconnected Ports

After doing P&R with Astro and save its hierarchical netlist as verilog file, you can find some unconnected ports generated at the input and/or output ports. If it is at the input port, that should be connected to VDD or VSS (I think it is usually connected to VSS). But if it is at the output port, that doesn't matter connected to VDD/VSS or not.

 

[A.Anand Srinivasan]

Re: Unconnected Ports

How this noise analysis & Signal integrity calculations are being done?.

it is just basic analysis of the noise coupling relative to the impedance...

 

[iwpia50s]

Unconnected Ports

You did not specify if this is the input/output of a cell or a module. If its a module and there are no cells connected to it, then both input and output can be left unconnected. If it is a cell then you must tie the input hi or lo, but the output can be left unconnected.