what the limitation of a high frequency buck?

[walkalways]

hi all, does anybody had done high frequency synchronous buck, what the limitation is? now, the spec is: vin 2.5v-5.5v, vout 0.8v-3.3v, frequency=4Mhz, i want to use peak-current-mode, but the blanking time will limit the minmum duty cycle. any good method can reduce the blanking time? or anyother better method?

 

[dick_freebird]

Your blanking time required depends on how clean the output switch
node waveform is. If somebody set that in the design then you are
stuck with their idea of worst case. But your stepdown ratio at worst
is 0.8/5.5 or 14.5%, and at 4MHz that is 36nS. That is probably
about 3 wire resonance periods and longer than a rise time
(one would hope) so you might only be dogged by some bond
wire induced jitter with a clean enough board layout.

What do you expect to gain from going to 4MHz? Few (like
none) of my customers want to go above 1MHz. You might be
thinking you'll get a better ripple result? Beware the poor SRF
and ESL of decoupling caps, it's tough to get any bulk caps
with much more than 1MHz SRF.

Switching losses will most likely change your mind in the end
if you care about efficiency.

 

[walkalways]

this buck is a low power, about 600mA output, and the efficiency not so bad, i want the maximum efficiency above 92%. and the reason of high frequency is small external components, good load transient and line transient.