What Should be the Synthesis circuit

[spartanthewarrior]

Hi All,

can any body tell me that the bellow

//------------------------
always @ (posedge clk)
begin
a = 1'b1 ; (Blocking)
end
//------------------------

Will it generate a Wire or (Flip-Flop)

 

[vikas_lakhanpal27]

Flop. The process or always block which works on posedge or negedge of a clock takes flop.
Also in ur case a is always assigned to '1' the synthsizer can simply tie a to '1'.Why to unnecessarily use a FLOP? Right?

 

[spartanthewarrior]

Will it synthesize a Flop or Wire.

 

[FvM]

A constant assignment to a signal (without concurrent assignments to the target value at other places) will synthesize nothing.

always @ (posedge clk) 
begin 
a = b ; (Blocking) 
end

would synthesize a Flipflop. The difference between blocking and nonblocking assignment is only relevant for the evaluation of succeeding expressions with a in the same clock cycle.

 

[nikhilindia85]

It will synh to a D-FF wih input as a 1.even though u write blocking statement it wl synth by asuming it as a non blocking statement