What next when Post-layout STA in PT have violations?

[hgby2209]

post layout sta

What next when Post-layout STA in PT have violations?
The following is our current solution:

Goto DC do back-annotate sdf, pdef, & set_load, set_resistance
--> create "Custom-Wire-Load-Model" --> Timing analysis(STA)
--> do reoptimize using "reoptimize_design" command --> netlist & sdc back
to APR

If goto this flow why need Primetime to do STA? DC can do STA, too.
And in this flow PT never pass any info. to DC to do reoptimize!!

Does anyone have any suggestion?

 

[davidyu]

timing violation post layout

PT is the sign off tool for sta, and also the sdf file from pt can be used to correlate the time annalsys for DC.

 

[kelvin_sg]

define p.t. sta.

Is it because PT is more accurate and faster than DC?
I usually use PT when I analyze timing from P&R, while
before sending netlist for P&R, I don't think it is necessary to do PT anyway.

 

[hahaguy2]

post of sta

you can fix the violations in placement step, by adding some tighter timing constraints, i dont think DC will help much

 

[wkong_zhu]

PT is more efficient and accurate than DC

 

[siawklai]

Depend on your margin...
if small, then I believed PnR tool able to handle... like changing floorplan, useful skew...
if big, then you may try to do advance compile technique like overconstraint, apply critical range, using DW & ungroup DW, using DC ultra compilation, disable low driving cell...
if still can't solved, then try change architecture design.
Hope this help

 

[haosg]

you need to carefully check the violation,
if the start and end point are in same clock domain, and they are very close,
and no too big transition violation in the path
I think you may need return to DC to do more effort .
PT is sign-off tool, and it can read spef for delay calculation.
it could not be replcace by DC.

 

[hgby2209]

Can anyone tell me, if you run Post-layout STA in PT and get some violations,
then how to fix it except DC?

 

[honeyxyb]

First , you should check the violations, to see why violations appear?
Maybe layout tools not complete fix all timing violations, so need layout tools
do it .
Secondly , To check you script, does the script correctly? And it's consistent with the scripts to layout tools, if the script is not the same , violations appearance
are not oddness.
If above two are correct, in normal case , you should not see violations.

Added after 8 minutes:

I think we can't use rising_edge or falling_edge timing type to descript combinational logic.
In Pathmill, I found if only define clock node as source_node , the lib file
will use negative_unate to descript invter, if define it as clock reference, will
use xxx_edge to descript inverter. But how to descript one invert should not
depend on the define of input node , so I'm so confused.

 

[maxsnail]

pt have more command, than dc can not do, pt and dc use same timing analyzer engine

 

[firendchn]

firstly, you need check the constraint correct or not.
then, rerun STA, if violation cannot be removed still, you must check your design.

 

[haosg]

I think that doing more effort in APR can fix most violation in STA,
you can increase setup / hold timing check margin in Astro.
if the constraint have error, you also find in APR stage and fix it.

 

[JasonMa]

I think PT is more efficient and faster than DC and most violations in post STA can be fixed by P&R tool.

 

[gaonkc]

if pre-layout sta violation, maybe can be fixed during P&R , if post-layout sta violation , must analysis to fix it.

 

[visualart]

in my opinion, you ought run the P&G with the delay information again.

 

[tigerliu]

Hi,
First, the driving engine of DC and PT isn't the same and the PC timing analysis engine is more powerful, althogh the priciple inside these two tools may be the same. In deep sub-micro design,like 0.13 process,DC is not the best choice .You have to use Physical Compiler,but you still can use PT to do STA. PT is the signoff tool, it you want to tapeout your chip, you have to use it.
Second, if you got violation in PT. First of all, check your constrains to see if you have correct constraints(Mostly happened). Then ,you may change your P&R if the slack is not too much (<15%). If P&R is not helpful, sitdown and talk with your RTL coder, maybe you need change your design. All need hard working and thorough thinking.
Waiting for more discussions.

tiger

 

[michealwolf]

How can I reoptimization the design in DC?
1. If use reoptimization-design command, is the PDEF(gate location information) necessary? can I do it without the PDEF?
2. After reoptimzation, we got a new netlist. Can Astro take this netlist to do an ECO flow based on the old result? If there are a large amount modification, Astro may can not handle it?
3. or Astro take the new netlist to do P&R from the beginning. If so, the netlist is optimized based on the old Back-Annotated data. Is that helpful with a new Astro running?
4. Can I use DC to generate a new netlist with updated constraint, in such situation.

Thanks a lot.