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Logic synthesis. Produces a netlist—logic cells and their connections.
System partitioning. Divide a large system into ASIC-sized pieces.
Prelayout STA. Check to see if the design functions correctly.
Floorplanning. Arrange the blocks of the netlist on the chip.
Placement. Decide the locations of cells in a block.
clock tree synthesis. making real clock to the design
Routing. Make the connections between cells and blocks.
Extraction. Determine the resistance and capacitance of the interconnect.(real RC values)
Postlayout simulation. Check to see the design still works with the added loads of the interconnect.
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