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Because DDR and DDR2 are SSTL2 signals that are compared against a reference, the term rise time is not really used. Instead, signals are measured in slew rate. Typical slew rate values are 1.5 to 5.0 V/nS. However, remember that valid signals only have to vary above and below the Vref by about 200mV.
DDR also have limits on overshoot and undershoot. Therefore, driving signals too hard can cause problems in those areas.
If you use SSTL2 drivers in the FPGA and do not fan out to a extremely large number of chips, then it is usually not an issue.
The slew rate data does not really affect signal trace length. In general, all traces within a group to the SDRAM are routed with matched delay. This insures that the signals all arrive at the memory at the same time. By a group, I mean signal group, like "address", "control" or "data". Depending on the clock or clocks within the FPGA used to drive the SDRAM interface, you may or may not also match delays between the groups. (Matched delays is a little different than matched length. Matched delays account for propagation differences on external vs internal layers, etc.)
Take a look at:
**broken link removed**
This NuHorizons app note takes you through the design process for interfacing DDR to a Xilinx Spartan.
No, I believe you are not thinking about how the signal really propagates. As a thought experiment, assume that we are driving out a triangle wave. At time t=0, the driving signal crosses v=0 and is ramping in a positive direction. Some time later the signal starts arriving at the load. What portion of the signal arrives first? Would we expect that the peak arrives first? No, the first thing to arrive is the first thing to be sent which is the linear ramp crossing through zero. Therefore, a signal cannot complete its transition while being propagated. Regardless of how long or short the line, it only arrives in tiny time slices exactly as it was sent. Now, it the line is NOT terminated in its characteristic impedance, or the line impedance changes abruptly during tranmission, then the result waveshape will be distorted.
If you can may the line very short compared to the rise time of the signal, then you can ignore some of the transmission line effects, but that is usually not practical.
To insure that data is captured correctly, SDRAM, DDR and DDR2 use a capture clock. It is only important that the sufficient setup and hold times exists between the data and this capture clock.
How do you assure the timing relationship between the data and the clock? By controlling the routing delays for the signals. Assume that the driver places the data and clock into the proper timing relationship. Then if both are routed on controlled impedance lines with the same delay, the signals will maintain the some phase at the receiving end.
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