What is the realistic clock jitter that my ADC has to be able to tolerate?

[jowong1]

Hi, i m designing a CT delta sigma ADC. I was wondering about the following,

1. Without using an on chip PLL, what is a realistic clock jitter that my ADC has to be able to tolerate?

2. How do I simulate clk jitter in simulink

Thanks

 

[mpig09]

Re: realistic jitter

Dear jowong1 :

for your first question:
1. Without using an on chip PLL, what is a realistic clock jitter that my ADC has to be able to tolerate?
==>I guess you need to know your setup time and hold time of S/H circuit.


mpig