what is the diffirence ?unsigned , std_logic_vector,integer

[vvsvv]

unsigned std_logic_vector

in my vhdl source code ,I use std_logic_vector,
i used a counter to counter number of pels, all the number should be positive number, however, there is nagtive number appear ,

what should I do ?
shall I change the data type from std_logic_vector to integer ?

-----------------------------------------
May I use "integer" type in my port declaring?

thank you very much!

 

[ramesh]

unsigned to std_logic_vector

Is there overflow in the counting? Check.

 

[vvsvv]

std_logic_vector to integer

what is meaning of "overflow" ? does it mean that the "std_logic_vector(18 downto 0)" have a MAX of
2**19 = 524288 ?

however , the number of my counter should be less than 524288 !?

what should I do ?

thank you!

 

[ramesh]

unsigned versus std_logic_vector

The "std_logic_vector(18 downto 0)" have a MAX of
(2**19 )-1. That is the range is 0 to 524287. You should not exceed beyond this. You can as well use UNSIGNED(18 downto 0).

 

[elektrom]

std_logic_vector unsigned

It's not recommend to use integer type for port declaration. Coz, finally the synthesis tools will convert in to std_logic_vector type for gate-level netlist. Use only std_logic or std_logic_vector on the top module is recommended!.

 

[rourabpaul]

what is the basic difference between std_logic and unsigned type??

 

[TrickyDicky]

a std_logic is a resolved type with 9 possible states.

an unsigned is a collection of std_logic that represent an unsigned integer
a std_logic_vector is just a collection of std_logic. It could be signed, unsigned, a load of control bits - you just dont know.

They are 2 completly separate types and have to be converted to be interchangable. The typing system is there to make it easier for everyone to know what you are trying to do.,

 

[scanman]

Check out this doc:
https://www.synthworks.com/papers/vhdl_math_tricks_mapld_2003.pdf

Cheers scanman