What is the difference between VHDL and Verilog?

[NTFS]

VHDL/Verilog

hi

what is the difference between VHDL and Verilog?

thanks.

 

[Jack// ani]

VHDL/Verilog

dude...its two different hardware description language.

https://en.wikipedia.org/wiki/Verilog

https://en.wikipedia.org/wiki/VHDL

 

[Sathish]

Re: VHDL/Verilog

hey,
Regarding this you can see this link



with regards,
sathish kumar

 

[saberbf]

Re: VHDL/Verilog

for begginers, verilog is easier than VHDL to learn and is recommended

 

[naveen reddy]

Re: VHDL/Verilog

Verilog and VHDL are the two different hardware description languages used in the present day industry

Verilog is easy to learn for beginners but VHDL is much robust that verilog
both the languages have there own strengths and weakness

In Europe VHDL is used extensively and in U.S verilog is used

 

[zharaa]

Re: VHDL/Verilog

VHDL and Verilog are languages for hardware design.
VHDL is ADA based and Verilog is C based language.
Some people find that Verilog is easier to learn, others find VHDL is more
powerful.

 

[salma ali bakr]

Re: VHDL/Verilog

look at this article:



u will find a link in it that discusses the differences in details
hope that helps ya...
take care,
Salma