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do u mean sparegate.the sparegates are having the interenal design like fpga basic cell.we can get some small logic from that.we will place some sparegates in each module and we will supply the clock,reset to the spare gate cell.the remaining pins we keep unconnected.so that we can connect those pins according to the requrement through the ecos.
while doing the synthesis we have to place the set_dount_touch arrgument on those cells.
Customer has given ECO cells schamtics to do layout, these ECO cells contains the straight poly and remaing are same like normal standard cells
I don't the applications of ECO, where exactly they will use and also i need clarification on Gate array cells (i.e ECO and Gate array cells are same)
If you mean spare cells, then these cells are strategically placed in layout but are not a part of any functional circuit. i.e they are not connected. These are used in case a respin is required ie some minor changes in layout is required to bug fix.
By using spare cells you can save base layer mask changes and only metal mask change can fix the bug. Hope this clarifies.
Hi Amara,
ECO cells can be used in PD flow to meet the timing. As you stated correctly it is the same as that of standard cell except a poly/metal layer so as to make desired connection to make it a functional cell. ECO cells are nothing but same as that of standard cells. They are spread through the chip so that if a cell is needed to make the timing correct, ECO cell can be used for that.
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