maitrey17
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Hey,
I am a new member on board. I ma a Grad student in Digital Design n working on project for ASIC Design.
In reply to your Question,
The QUestion is really a broad minded. In Digital Design if you are talking about FPGA's and ASIC's then,
Die - yield.
Signal Integrity and Crosstalk.
Heuristic Algorithms that work behind the EDA Tools and give you the "supposedly" optimum Placement- Partitioning- Routing - Floorplanning Solution is also a big deal these days. Because not one particular Algorithm works and any kind of problem. So this makes Physical Layout harder and harder.
Above all this, I believe most imp. topic right now is "where is the end of the ever increasing process technology?" Right now we are moving towards 65nm technology where , NONE of the Industry EDA TOOLS have the capability to become compatible with 65nm technology where we are moving. All EDA tools have been built only uptill 90nm technology. So, when we move our forces for 65nm, we already have crosstalk and signal integrity issues in 90nm so think about it in 65 nm. Also, the yield is very very less at preset....so think what will it be at 65nm.....
I believe that this is the biggest Revolution as far as every single thing is concerned. all eda tools have to be re designed and all algorithms have to be re considered. in this process, there are few leading companies that are having a hard time with this all issues.
I am a new member on board. I ma a Grad student in Digital Design n working on project for ASIC Design.
In reply to your Question,
The QUestion is really a broad minded. In Digital Design if you are talking about FPGA's and ASIC's then,
Die - yield.
Signal Integrity and Crosstalk.
Heuristic Algorithms that work behind the EDA Tools and give you the "supposedly" optimum Placement- Partitioning- Routing - Floorplanning Solution is also a big deal these days. Because not one particular Algorithm works and any kind of problem. So this makes Physical Layout harder and harder.
Above all this, I believe most imp. topic right now is "where is the end of the ever increasing process technology?" Right now we are moving towards 65nm technology where , NONE of the Industry EDA TOOLS have the capability to become compatible with 65nm technology where we are moving. All EDA tools have been built only uptill 90nm technology. So, when we move our forces for 65nm, we already have crosstalk and signal integrity issues in 90nm so think about it in 65 nm. Also, the yield is very very less at preset....so think what will it be at 65nm.....
I believe that this is the biggest Revolution as far as every single thing is concerned. all eda tools have to be re designed and all algorithms have to be re considered. in this process, there are few leading companies that are having a hard time with this all issues.