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Gate oxide leakage can be better explained by quantum theory. Basically, carriers can be easier to penetrate through the thinner oxide (energy barrier).
but i want to know how much current will penetrate the gate oxide, can this effect be comparable to reverse diode current or substrate current? i.e. we need to consider it?
mos transistor parameters are not scaled down with the device dimension and that causes many problems.
1. kt/q doesn't scale down. this causes a big problem => when transistor in subthreshold region, the current is nonzero, which results in current leakage and in turn power dissipation.
2. bandgap of silicon doesn't scale down. this doesn't directly affect circuit performance.
3. quantum tunneling effect. this also causes current leakage problem but it's not been totally understood or solved yet.
there are few component on the leakage current in a transistor...
1. reverse bias current (between drain/source & bulk).
2. gate leakage.
3. and another two more component (i forget).
but in current (not so current anymore) 65nm, the gate leakage is the worst one (the dominant)... as the gate oxide thickness is just few atomic layer, electron go through it easily...
there are few component on the leakage current in a transistor...
1. reverse bias current (between drain/source & bulk).
2. gate leakage.
3. and another two more component (i forget).
but in current (not so current anymore) 65nm, the gate leakage is the worst one (the dominant)... as the gate oxide thickness is just few atomic layer, electron go through it easily...
it is simple, holddreams, gate leakage is the current flows through the gate to the source/drain/bulk because of a very thin layer of oxide (the insulator).
for instance, for an NMOS, when u put a 0V on the "gate" and VCC on the "drain" and ground the "source"... the transistor should be in the off mode and ideally no current flows in any node.
but actually the current from the "drain" (VCC) will flow through the oxide to the gate with lower potential on the 0V (gate), and some through the "source" from the "drain"... major static leakage is through the gate for 65nm...
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