What events are not synthesizable in Verilog?

[ASIC_intl]

It is said events are not synthesizable in verilog. What are these events?
Provide some specific examples.

 

[jbeniston]

events in verilog

An event that is sensitive to multiple clock edges most likely isn't synthesizable:

always @(posedge clk1 or posedge clk2)

 

[ASIC_intl]

Re: events in verilog

It is said that "Events are not synthesizable". Probably these are not the events like @(posedge clk) when this comment "Events are not synthesizable" is written.

 

[sree205]

events in verilog

by events, it means, something like this

when en==1'b1
-> start_an_event.

this event can be used as jbeniston says in the always block.

always@(event_started)
do something


these events which are started in verilog code can't be synthesized. Hope i've been clear. Incase of any more clarifications, do let me know.

 

[ASIC_intl]

Re: events in verilog

Hi sree 205

Do u mean that posedge/ negedge are not events?

 

[sree205]

events in verilog

they are also events, but they r just not the events that are not synthesizable. Generally, the rule of thumb is that, posedge/negedge clocks are synthesizable, coz, the tools are intelligent to understand them and synthesize a flop, where clock edge is necessary. Hope i've been clear enough.

 

[madhavisai]

events in verilog

A changa on input is treated as event in verilog

 

[krishanu007]

Re: events in verilog

events here( which is being told as non-synthesizable)are part of verilog code....
they are added for simulation purpose.they can be created & triggered conditionally.
like..
event job_done;

always@(a,b)
begin
if(a==1 && b==2)
->job_done; //this triggers the user defined event.
end