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For digital design, these ever smaller dimensions/technologies apply. Analog has been stuck on L around 1-2 um for a long time. Problem with .13 um or smaller technology in analog design is that short channel effect (2nd order effect) begin to emerge and things get a lot messier when you sit down and design. Models and assumption made in analog are no longer valid.
Because now there is almost no pure analog circuit, so the narrower length can be used for the digital circuit use , and the narrower length process has lower Vth for lower power design.
Need to be careful here.
The "0.13um" always refers to the smallest gate available to that technology, but not the smallest feature size. e.g. the LDD spacer for a 0.13um transistor could be as small as 20nm, in a certain 0.5um BiCMOS process, the smallest feature is a 8nm trench surrounding the emitter.
However there are differences on what is the smallest Gate:
For foundries, like TSMC, UMC and Chartered Semi, the 0.13um refers to the smallest gate width (L) printed on the chip. So Leff is close to 0.10um
Certain IDM's like Motorola, the 0.13um refers to the smallest Leff so for example, in their 0.35um process, the minimum gate width printed on the wafer is 0.40um.
Intel do this also.
As you have questioned about 0.13µm technology, it's actually 0.12µm (to be exact). 0.12µm is specified for the Poly-Si Gate of a MOS transistor in the HCMOS 9 Technology officially adopted since 2000 by all foundaries and IC Fabrication Facilities.
As you can see, it only specifies the Poly-Si Gate of a MOS Transistor, i.e. only the Masked Gate Length. Thus not the Effective Gate Length, which is subjected to Lateral Diffusion on either side of the channel in the 7-layer CMOS Process of a HCMOS 9 Technology. If to use the Effective Gate Length as a standard, this will make the control of CMOS process too difficult to manufacture millions of MOS transistors on the same wafer at a high yield by any IC Fabrication Facilities.
For over the past decade, all Digital ICs are designed using CAD Software on workstations. Designs are subjected to Grids and Pitches specified in a chosen HCMOS Technology. In this manner, the physical layout of an IC design can be produced in a universal or standard specifications so that it can be manufactured the same way anywhere, from North America, Europe and Asia.
Before 0.12µm, there were 0.25µm and 0.5µm. All these are collectively known as the Lambda-based designs that were widely accepted since 1985 used in the IC community. This further promotes Design Re-use Concept.
PhD (Imperial College London)
IC Design Engr. Analog Devices Plc. (Ireland)
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