narureddyk
Newbie level 6
Does the "elaborate design" in LEC do any synthesis? does it generate any netlist?because in my lec dofile has the following steps
read design .............
elaborate design -golden
set root module abc_core -golden
read design -verilog
xyz_lec.v
-revised -lastmod
set root module abc_core -revised
Can any one explain what this lec step is doing and whuch netlistls it is comparing?
read design .............
elaborate design -golden
set root module abc_core -golden
read design -verilog
xyz_lec.v
-revised -lastmod
set root module abc_core -revised
Can any one explain what this lec step is doing and whuch netlistls it is comparing?