What does "#" do in verilog code ?

[sameh_yassin99]

Hi,

I use the following code to implement a generic shift register.

/////////////////////////////////////////////
module Equalizer_IP(parallel_o,serial_in,clk_in,enable,reset_in);
   parameter filter_order = 7;
	parameter bw = 4;
   parameter maxbitgain = 21;
   
   output  [bw-1:0] parallel_o;
	input [bw-1:0] serial_in;
   input clk_in;
	input enable;
	input reset_in;  
	
	reg [bw-1:0] pipeline [0:filter_order-1];
	integer i;
/////////////////////////////////////////////   

assign parallel_o = pipeline[filter_order-1];

always @(posedge clk_in) begin
		pipeline[0] = serial_in;
		for(i=1;i<filter_order;i=i+1)begin
			pipeline[i] <=  #3 pipeline[i-1];
		end
	end
/////////////////////////////////////////////   

endmodule // end main

The output is just fine as shown in the following image,

It works as desired but I don't understand what the symbol "#" do. The symbol makes no difference.
It is used in the OpenBTS project in many positions so I need to know what does i do.

regards,

 

[FvM]

It's a delay statement that takes affect in simulation only. It refers to the default time unit, usually ns.

 

[sameh_yassin99]

Hi,
I dunno what do they use it allover the design files. I think having so many "#" inside the design files gives the impression of "spaghetti" coding, although the code is very well structured.

 

[FvM]

Depends on the code's purpose. If it's a simulation model, delay statement would be reasonable.

There's also a different usage of # with parameters in module instantation.

 

[sameh_yassin99]

Hello,

Can u please give an example for the use of "#" for synthesis..

 

[rberek]

I have seen some coding styles that require some small delay in them to simulate correctly, because without the delay a race condition will ensue and the simulation will not be correct. Looking at the code above, I can see why the delay might be necessary. Each element of the pipeline is loaded with the previous element using a non-blocking statement. Without the delay, each stage of the would be loaded simultaneously in simulation and there is a chance the simulator will not reflect what is supposed to happen.

r.b.

 

[FvM]

Without the delay, each stage of the would be loaded simultaneously in simulation and there is a chance the simulator will not reflect what is supposed to happen.

May be the author of the code was stuck in the same misunderstanding of Verilog behaviour. Actually the evaluation rules for non-blocking statement will be sufficient to achieve correct behaviour of the pipeline construct. The LHS of the assignment will be updated at the end of the clock cycle, after the iteration and the always block have completed.

---------- Post added at 18:18 ---------- Previous post was at 18:06 ----------

Can u please give an example for the use of "#" for synthesis..

The only meaningful usage for synthesis I'm aware of is for module parameters (old module parameter syntax). Example from the IEEE Std 1364:

module generic_fifo
#(parameter MSB=3, LSB=0, DEPTH=4)
//These parameters can be overridden
(input [MSB:LSB] in,
input clk, read, write, reset,
output [MSB:LSB] out,
output full, empty );

 

[rberek]

I stand coirrected!

However, it is still true that I have had the displeasure of using and debugging supposedly synthesizeable code which did not simulate correctly without benefit of small delays. Debugging usually meant rewriting.

r.b.

 

[FvM]

Standard simulation is functional simulation, where all logic element delays are ignored. Simulation of synchronous designs should regularly work without auxilary delay statements. External interfaces and modelling of periperals devices may require it, also stimulus generation of course. Personally I never used delay statements in the design or unit under test, only in the testbench itself and simulation models.

 

[rberek]

I agree. I have never used delays in synthesizeable code either.

r.b.